1. Field of the Invention
The present invention relates to an integrated circuit and more specifically to its power supply network.
2. Discussion of the Related Art
FIG. 1 is a simplified view of an integrated circuit 1 conventionally comprising a peripheral ring-shaped assembly 2 formed of input/output blocks. Integrated circuit 1 comprises several functional blocks: a microprocessor 3, a SRAM 4, an amplifier 5, a phase-locked loop circuit PLL 6, and a ROM 7. The functional blocks of circuit 1 are interconnected by an assembly of so-called “global” connections intended to transmit signals between the blocks such as a clock signal which is provided by PLL circuit 6 to each of the other functional blocks. Further, each functional block may be formed of sub-blocks, which are shown in dotted lines in microprocessor 3, interconnected by a set of connections specific to each block. The input/output blocks of peripheral ring-shaped assembly 2 and functional blocks 3 to 7 are connected to ground GND and to a supply voltage VDD by a power supply network, which will be described in further detail hereafter.
Generally, the connections specific to each block, the global inter-block connections, and the power supply network belong to the integrated circuit interconnection network. Such an interconnection network is, in practice, formed of several levels of conductive tracks separated by conductive via levels. Each track or via level corresponds to an assembly of metal tracks or vias placed in openings of an insulating layer. Number N of conductive tracks is variable from one integrated circuit to another. Integrated circuits comprising five or six levels of conductive tracks can frequently be encountered. The connections specific to each block of the integrated circuit are generally formed in the lower track levels, the upper levels being reserved for the placement of a general power supply mesh formed of an assembly of rails partly connected to supply voltage VDD of the circuit and partly connected to ground GND.
FIG. 2 is a simplified view of the power supply mesh of integrated circuit 1 shown in FIG. 1. The power supply mesh comprises an assembly E1 of vertical parallel rails E1, shown by hatchings, and placed at the last track level N of the integrated circuit interconnection network. The mesh further comprises an assembly E2 of horizontal rails placed at the penultimate track level, that is, N−1. Among level E1 of vertical rails, one rail out of two is connected to ground GND and one rail out of two is connected to supply voltage VDD. Similarly, among assembly E2 of horizontal rails, one rail out of two is connected to ground GND and one rail out of two is connected to supply voltage VDD. The rails of assemblies E1 and E2 are connected to one another by an assembly of conductive vias, shown by full disks, and placed at the intersections in top view of a rail of assembly E1 and of a rail of assembly E2. The rails of assemblies E1 and E2 connected to supply voltage VDD are connected to one another and those which are grounded are connected to one another.
To decrease as much as possible the resistivity of the power supply mesh, the tracks of the last and of the penultimate track level are generally provided to be relatively thick, and often thicker than the tracks of the lower levels. Further, the supply rails often are as wide as possible and closely spaced together. It is however sometimes necessary to limit the bulk of the rails of the power supply mesh to be able to slide a few global connections between these rails when the integrated circuit is particularly dense or when a limited number of track levels is available.
The way in which functional blocks 3 to 7 of the integrated circuit are connected to the general power supply mesh is described hereafter in relation with FIGS. 3 and 4.
FIG. 3 is a simplified view of the integrated circuit shown in FIG. 1 in which functional blocks 3 to 7 are shown in dotted lines. Each functional block comprises an assembly of parallel supply rails placed in track level N−2 of the integrated circuit. In this example, the rails of blocks 3, 6, and 7 are vertical and the rails of blocks 4 and 5 are horizontal. For each block, one rail out of two is intended to be connected to ground GND and one rail out of two is intended to be connected to supply voltage VDD of the circuit.
Conventionally, the design of the interconnection network of an integrated circuit, prior to the manufacturing of a set of masks used for the effective manufacturing of the integrated circuit, is performed by means of computer-assisted design tools, according to the following method.
Each functional block is prepared. For this purpose, an assembly of parallel rails is placed on the upper portion of the block in track level N−2 above the block elements. One rail out of two is intended to be connected to supply voltage VDD and one rail out of two is intended to be grounded. The supply rails are then connected to the various elements of the considered block. The connections specific to this block are then routed, that is, the connections connecting the various block elements in track levels 1 to N−3 are placed.
Once all the functional blocks have been thus prepared, the different blocks are placed on the integrated circuit surface. The selection of the location and of the orientation of each block is a function, among others, of its bulk and of its shape. In this example, blocks 3, 6, and 7 are “straight” and blocks 4 and 5 are “rotated”, a block being straight or rotated according to whether its supply rails are respectively vertical or horizontal in the considered drawing.
Once the integrated circuit blocks have been positioned, a general power supply mesh, such as that shown in FIG. 2, is placed above the integrated circuit blocks. This general power supply mesh is then connected to the assemblies of supply rails of each of the blocks according to the method described in further detail hereafter.
FIG. 4 is a simplified view of previously-described integrated circuit 1 showing the elements shown in FIG. 3 and in which are shown the assembly of rails E2 of the power supply mesh shown in FIG. 2. The assembly of rails of power supply mesh E2 is formed in track level N−1, that is, just above track level N−2 where the assemblies of the supply rails of block 3 to 7 are placed. For clarity, the assembly of rails E1 placed at the level of tracks N has not been shown. For each of blocks 3 and 7, the assemblies of supply rails are substantially perpendicular to the assembly of rails E2 of the general power supply mesh. In this case, it is possible to easily connect the rails of each block to rail assembly E2 by placing conductive vias at the level of each intersection in top view of a rail of a block and of a rail of assembly E2 both intended to be connected either to ground or to supply voltage VDD.
As concerns “rotated” blocks 4 and 5, complementary vertical rails 41 and 42 are positioned respectively to the left and to the right of block 4 and complementary vertical rails 51 and 52 are placed respectively to the left and to the right of block 5. For each of blocks 4 and 5, horizontal extensions of one supply rail out of two are provided leftwards to reach complementary rails 41 and 51 and horizontal extensions of one supply rail out of two rightwards to reach vertical complementary rails 42 and 52 are provided. Complementary vertical rails 41, 42, 51, 52 are then connected to rail assembly E2 of the general power supply mesh by the placing of vias at the intersections in top view between a complementary vertical rail and a rail of assembly E2 both intended to be either grounded or connected to supply voltage VDD.
As visible in FIG. 4, the non-rotated functional blocks are connected by a large number of vias to the general power supply mesh while the rotated blocks are connected by a limited number of conductive vias to the general power supply mesh. Further, rotated blocks 4 and 5 are connected to the general power supply mesh by their ends, which results in significantly increasing the resistance of the power supply network at the level of each of the rotated blocks.